1. Field of the Invention
The present invention relates to a semiconductor passive component, and more particularly to an integrated inductor structure.
2. Description of the Prior Art
Along with the recent trend of system-on-a-chip (SoC) design for IC manufacturing, passive components such as integrated inductors or integrated transformers have been fabricated on high-frequency integrated circuits instead of being external components. It is known that substrate loss and losses due to the series resistance of the inductor's conductive path (which increase with increasing frequency of operation) have been found to adversely affect the quality factor Q.
Some prior art methods such as those disclosed in U.S. Pat. Nos. 6,593,838, 6,756,656, and 7,084,481, the contents of which are incorporated herein in their entirety by reference, teach using patterned ground shields, which are composed of polysilicon or metal, to reduce the eddy current, thereby increasing the quality factor.
However, such approaches, i.e., using polysilicon or metal patterned ground shields to reduce the eddy current, increase parasitic capacitance or displacement current of the integrated inductor and as a result reduce the self-resonance frequency, which adversely affect the applicable frequency range of the inductor component.